Shobha Vasudevan is an associate professor in the department of Electrical and Computer Engineering, and an affiliate in Computer Science at the University of Illinois at Urbana-Champaign. Her research interests span reliability of systems and machine learning algorithms. She has won several best paper awards including one at DAC 2014, one at VLSI Design 2014 and several best paper nominations. Her other honors include the NSF CAREER award, ACM SIGDA Outstanding New Faculty Award, IEEE CEDA early career award, IBM faculty award, Dean’s award for research excellence in UIUC, and a YWCA/UIUC award for service to women in engineering. GoldMine, a verification software from her group has been developed into a commercial product since 2014 and has been licensed by multiple semiconductor and electronic design automation companies from UIUC. She conceptualized MyTri, a professional networking portal for women engineers in UIUC. She is a technical consultant for several companies. She enjoys mentoring young women engineers and scientists, and young women who can be future engineers and scientists.
M.S: Electrical and Computer Engineering, The University of Texas at Austin
B. E: Bachelors in Computer Engineering, University of Mumbai, India
Google Faculty Research Award 2019
Invited talk at Facebook Virtual Reality Labs
Talk on GoldMine and beyond: Scaling verification with machine learning. Great questions and discussions.
Best paper nomination at ASP-DAC 2019
Our paper, “A Figure of Merit for Assertions in Verification” was one of the nominated papers for the best paper award at ASP-DAC 2019. The paper presents computable metrics to find the goodness of human written and machine-generated assertions. The paper attempts to answer the question of how good the specification of a system is. Assertion quality metrics can be used for design understanding, coverage analysis and debugging. The tool for assertion metrics is available for download here.
Invited tutorial at VLSI Design 2019
Shobha gave an invited half day tutorial on DUPLEX, our optimization tool. The talk had new results from applying DUPLEX to computer vision and perception problems. DUPLEX works better than gradient descent in our preliminary results. Great audience- gave ideas for lots of new applications for DUPLEX!
Women In STEM forum
Prof Vasudevan was a panelist for a women in engineering forum to discuss increased participation of girls and women in STEM fields in India. The event saw a participation of more than 300 people. Encouraging. The panel was on women retaining their jobs, given the sharp drops observed mid-career.
Machine learning applications book chapter by Shobha
Machine learning and AI has made its way into manufacturing and electronic design automation in a big way. Watch out for Prof. Vasudevan’s new chapter in the book on ML4CAD by Springer , due to be published in Spring 2019. Thanks to editors Ibrahim Elfadel, Duane Boning and Xin Li for putting together a timely topic.
New kind of error out to get us in our cars!
We uncovered a new class of soft errors caused by electrostatic discharge. We fabricated a test chip and measured corruptions in apps and programs running on the chip when a physical ESD gun shoots at the chip. We find that these are particularly prevalent and widespread in automotive environments. The biggest threat from these errors is to microcontrollers in ESD rich zones like highly autonomous vehicles. An error in our cars could have serious consequences.
Watch out for our forthcoming paper in DATE 2019, Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors.
Talk at Haifa Verification and Privacy Conference
Prof. Vasudevan gave an invited talk at the Haifa ViPs conference, a new incarnation of the Haifa Verification Conference (HVC). Quality of invited talks was excellent. As was the audience. Thanks to IBM for the invitation!
Best paper nomination at DAC 2018
The apps you use can shape how bug free your phone is! Our paper Application-level hardware tracing for scaling post-silicon debug by Debjit Pal and Vasudevan was nominated for a best paper award at DAC 2018. This presents an approach to analyze SoC hardware for mobile devices using formal modeling of app-level information. The paper was the result of a long and productive collaboration with both Intel and IBM. The app-level analysis scaled up the silicon debug to a large, real life SoC as opposed to small benchmarks. We want everyone to use it, so we put it here.
My research interest is in algorithms for analysis at scale. I am interested in solving complex real world problems in computing whose solutions are difficult to scale. In my research group, we apply our research to solve problems in hardware and software verification, computational genomics, enterprise security, cloud reliability, automotive validation, autonomous vehicle and robot path planning, health care and neural network architecture reliability. In each case, the algorithms we have invented have been different- search, modeling, optimization, formal methods, causal inferencing, feature engineering, supervised and unsupervised learning among many others. We innovate with the purpose of solving high impact problems of tomorrow.
Verification and Reliability
Data science and machine learning
Ongoing and future directions
These are the challenges we are currently thinking about. If you want to collaborate with us or join our research group, please send me an email with a brief description of yourself and where you see a potential opportunity.