Our paper “Emphasizing Functional Relevance Over State Restoration in Post-silicon Signal Tracing” establishes insufficiency of the state-of-the-art metric called State Restoration Ratio (SRR) to evaluate trace signal quality. It also presents a new post-silicon trace signal selection algorithm based on  PageRank. This paper demonstrates that optimizing SRR typically generates signals that are functionally irrelevant to the design and unusable for …

The quality of the assertions is critical to the confidence and claims in a design’s verification! Our paper  A Figure of Merit for Assertions in Verification by Sam Hertz, Debjit Pal, and Shobha Vasudevan was nominated for the best paper award at ASP-DAC 2019. This presents an approach to rank assertions based on the key parameters that human beings look for to quantify “goodness” of …

Prof. Shobha Vasudevan gave a presentation on “Verification in the era of machine learning” at the International Conference of Rebooting Computing. Read my paper here.

Prof. Shobha Vasudevan gave a talk on self-driving cars titled “(Self)-driving up the wall: how many million miles of test driving will convince us.” Had an enthusiastic audience.

Prof. Shobha Vasudevan gave a talk on “Trust and security in systems today” at IBM Haifa ViPS 2018 .

Prof. Shobha Vasudevan will be giving an invited tutorial talk on analog validation. Talk title “The black art of analog validation”

Prof Shobha Vasudevan appointed as Associate Editor of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) from 2016-2018. Please submit your good papers to us!

Seyed Nematollah Ahmadyan (Adel) defended his thesis in front of a distinguished committee (Rob Rutenbar, Xin Li, Sayan Mitra, Martin Wong) with flying colors! What started as an analog verification and testing PhD, morphed into an optimization PhD by the time we were done! Adel’s DUPLEX algorithm is a randomized tree based search/sampling algorithm that can create directed analog stimulus, the worst …

Our paper “Application Level Hardware Tracing for Scaling Post-Silicon Debug” was nominated for the best paper award at DAC 2018. The paper demonstrates for the first time in published literature in post silicon in hardware tracing, an alternate viewpoint that can make the analysis scale up from tiny benchmarks to a real life SoC environment of the OpenSparc T2. It …

I gave a talk at Google Inc. in the Google Brain hardware group on current research in the group. Exciting directions.

I will be visiting the CS department at Stanford University in 2017. Looking forward to interacting and collaborating with my host Prof Subhashish Mitra and other faculty.

Prof. Shobha Vasudevan awarded the IBM faculty partnership award 2017 for post Silicon validation of many core systems

Sai Ma, winner of the DAC 2014 best paper award, graduated with an M.S. and joined Apple Corporation in the verification team. Rui Jiang with novel work on ESD induced reliability joined Apple as well as did Tian Xia with an M.S. thesis on neural network hardware implementation.

Jiayi Duan from our group finished a master’s thesis on “Feature Engineering for Detecting Security Compromises in Enterprise Log Data”. He used a creative method based on Fourier Transforms to get more than 70% increased malicious recall on real enterprise log data. He will be working on machine learning problems in Amazon Inc. starting July 2016.

Our paper, “Can’t see the forest for the trees: State restoration’s limitations in selecting signals for post-silicon debug” was nominated for best paper as one among 3 in ICCAD 2015. A journal paper will follow, demonstrating the scale of our technique on the OpenSparc T2.

Our papers “Formal probabilistic timing verification in RTL” and “Mining Hardware Assertions With Guidance from Static Analysis” cover two diverse aspects of hardware verification. Read and enjoy!

The award is given by ACM SIGDA to one junior faculty member who displays outstanding potential as an educator and/or researcher in the field of EDA. Many thanks to my students and collaborators for their role in this recognition. Pictures of the award ceremony can be found here.

Shobha Vasudevan named as the 2014 recipient of the IEEE Council of EDA Early Career Award.

Our paper “A Coverage Guided mining Approach for Automatic Generation of Succint Assertions” was awarded the best paper award at the VLSI Design conference 2014. Yet another GoldMine victory! The authors are Shobha Vasudevan, Lingyi Liu, David Sheridan and Hyung Sul Kim. An article appeared on the ECE website on it.

“Code Coverage of Assertions Using RTL Source Code Analysis” by Viraj Athavale, Sai Ma, Sam Hertz and Shobha Vasudevan. This paper generates a code coverage metric for assertions using dynamic and static analysis techniques. Attend our presentation at DAC 2014!

Automatic Generation of System Level Assertions from Transaction Level Models. Lingyi Liu and Shobha Vasudevan. Accepted. To appear in Journal of Electronic Testing: Theory and Applications (JETTA)

GoldMine is now available for academic and research purposes for free download. Please use for intended and new applications and give us your feedback! If you need GoldMine for a commercial purpose, please write to Prof. Shobha Vasudevan for an evaluation license.  

Parth Sagdeo et al’s paper “Using Automatically Generated Invariants for Regression Testing and Bug Localization” introduces a novel bug localization methodology with PREAMBL, a predicate clustering and invariant guided tool. Invariants from PRECIS in ASE 2011 are used for software regression testing as well.