Analog and mixed-signal designs are rapidly becoming all pervasive in mobile computing , security, health monitoring and automotive systems. Out of 28 chips in the iPhone5, 20 of them are analog/mixed signal based! The design processes are very complicated in these domains as compared to digital design, due to the nonlinear behavior, continuous state spaces, as well as the traditional method of physical optimization-based notions of correctness. Most of the current practice in analog designs is ad-hoc, random simulations. Analog CAD has not seen wide adoption, due to a very intuition-centric design methodology in analog. Monte Carlo simulations, that are a de facto gold standard for analog behavior simulation, fall very short of providing a validation environment. A validation conducive methodology must provide an ability to generate input stimulus, control the type of simulations, specify desired constraints or trigger events, as well as provide debugging, diagnosis capacity and a method to evaluate the test coverage
Rapidly-exploring random trees (RRTs) are data structures used for robot motion planning. The algorithm to build these data structures is a simulation of nonlinear behavior in continuous spaces. We have extended the RRT with the ability to specify goal regions or interesting regions in the state space, and bias the simulations towards those regions. We are also able to guide the simulation to cover more of the state space than in regular RRTs. We have specified and monitored properties using RRTs during runtime. We would like to specify properties in the frequency domain and monitor them, instead of the time domain analysis from the digital world that is not natural to analog specifications. We have developed a formal verification algorithm for analog using polytope reachability analysis.
And so what:
We are working on debug and diagnosis of sources of variation and noise in analog circuits. Our vision and long term goal is to theoretically analyze the RRT and generate bounds and confidence estimates that would help replace the traditional Monte Carlo simulations with the RRT-based validation paradigm. We are extending the methods and models using RRTs to mixed signal designs. The broader impact of this solution is to provide a “foot in the door” for algorithmic CAD/EDA methodologies into the analog design house. Our verification methodology is simulation based, and therefore scalable (although incomplete) and accessible to the analog designer. It can be built on SPICE as well as Verilog AMS levels.
This work is being done in collaboration with Texas Instruments and Intel Corporation.
- Seyed Nematollah Ahmadyan, Jayanand Asok Kumar and Shobha Vasudevan, Goal-oriented stimulus generation for analog circuits, Design Automation Conference (DAC) 2012: 1018-1023
- Seyed Nematollah Ahmadyan and Shobha Vasudevan, Reachability Analysis of Nonlinear Analysis through Iterative Reachable Set Reduction, Design Automation and Test in Europe (DATE) 2013: 1436-1441
- Seyed Nematollah Ahmadyan and Shobha Vasudevan, Efficient Stochastic SAT Solving Using Random Graphs. Invited paper in Workshop for Constraints in Formal Verification (CFV), 2013
- Seyed Nematollah Ahmadyan and Shobha Vasudevan, Runtime Verification of Nonlinear Analog Circuits Using Incremental Time-Augmented RRT Algorithm, Design Automation and Test in Europe (DATE) 2013: 21-26