Verification is a problem that is incredibly resource hungry, and has an incredibly small fraction of resources it actually needs. Hence all verification is a battle of scale. With hardware becoming faster, leaner, lower power, smaller and more versatile, every added feature brings complexity with it. It also brings a massive verification cost.
We will never be able to check all states in a modern system- whether it is a hardware, software or embedded system, since there are billions of states and not enough compute to check them. So the next best thing is to check whatever we can by simulating real behavior with tests. The quality of these tests, therefore is critical. They need to cover all important behavior, be succinct, detect bugs in the system and be fast.
Our work with HYBRO was the first of several tools that relied on branch-based coverage using formal methods to generate tests. Multiple commercial EDA tools collaborated with us and applied this principle thereafter.
Our algorithm using MORRTs (Multiple Objective RRTs) was the first technique to provide a goal oriented testing approach to analog simulations. Prior to that, Monte Carlo, which is a random simulation, was being used. The directionality in MORRTs comes from applying a goal/search objective to the RRT (rapidly exploring random tree) algorithm from robot motion planning.
Our worst case input stimulus “eye diagram” generation was nominated for a best paper award in DATE 2015. We have collaborated with Intel in developing the eye diagram solution.
Our algorithms and tools generate high quality tests for digital hardware, analog and mixed signal systems and SoCs. With HYBRO, we can generate corner case tests across a majority of the paths using assistance from formal methods like SMT solvers and symbolic state caching. We modified and repurposed a very well known algorithm from robot motion planning called the RRT, with directionality. We can generate “eye diagrams” or worst case behaviors for mixed signal systems that are much worse than what is generated by (accelerated) Monte Carlo simulations.
- Lingyi Liu and Shobha Vasudevan Efficient validation input generation in RTL using hybridized source code analysis, Design Automation and Test in Europe (DATE) 2011: 1596-1601
- Seyed Nematollah Ahmadyan, Jayanand Asok Kumar and Shobha Vasudevan, Goal-oriented stimulus generation for analog circuits, Design Automation Conference (DAC) 2012: 1018-1023
- Seyed Nematollah Ahmadyan, Shobha Vasudevan, Eli Chiprout, Chenjie Gu and Suriyaprakash Natarajan, Fast Eye Diagram Analysis for High-Speed CMOS Circuits. Design Automation and Test in Europe (DATE) 2015: 1377-1382. Best paper nomination (6 out of 600).
- Lingyi Liu and Shobha Vasudevan STAR: Generating Validation Inputs by Static Analysis of RTL, International High Level Design Validation and Test Workshop (HLDVT) 2009: 32-37
- Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan Towards coverage closure: Using GoldMine assertions for generating design validation stimulus, Design Automation and Test in Europe (DATE) 2011: 173-178
- Seyed Nematollah Ahmadyan and Shobha Vasudevan, Automated Transient Input Stimuli Generation for Analog Circuits. IEEE Transactions on CAD of Integrated Circuits and Systems (IEEE TCAD) 35(5): 858-871 (2016)